Realization and comparative analysis of thermometer code based 4-bit encoder using 18 nm FinFET technology for analog to digital converters CS Pittala, V Parameswaran, M Srikanth, V Vijay, V Siva Nagaraju, ...
Soft Computing and Signal Processing: Proceedings of 3rd ICSCSP 2020, Volume …, 2021
45 2021 High speed energy efficient multiplier using 20nm FinFET technology VR Ratna, PC Shaker, S Sadulla
Chandra and M, Divya and Sadulla, Shaik, High Speed Energy Efficient …, 2020
45 2020 Universal shift register designed at low supply voltages in 15 nm CNTFET using multiplexer RR Vallabhuni, M Saritha, S Chikkapally, V Vijay, CS Pittala, S Shaik
International Conference on Emerging Applications of Information Technology …, 2021
37 2021 FinFET Technology in Biomedical-Cochlear Implant Application SSVV Hima Bindu Katikala
International Web Conference on Innovations in Communication and Computing …, 2020
34 * 2020 HIGH PERFORMANCE 2:1, 4:1 AND 8:1 BINARY AND TERNARY MULTIPLEXER REALIZATION USING CNTFET TECHNOLOGY SS Vallabhuni Vijay, P. Chandra Shekar, V. Siva Nagaraju, S. China Venkateswarlu
Journal of Critical Reviews 7 (6), 1159-1163, 2020
27 2020 Applying several soft computing techniques for prediction of bearing capacity of driven piles S Shaik, KSR Krishna, M Abbas, M Ahmed, D Mavaluru
Engineering with Computers 35, 1463-1474, 2019
24 2019 Design and implementation of an automatic beverages vending machine and its performance evaluation using Xilinx ISE and Cadence VVSV Krishna, A Monisha, S Sadulla, J Prathiba
Computing, Communications and Networking Technologies (ICCCNT),2013 Fourth …, 2013
23 2013 Performance evaluation of different SRAM topologies using 180, 90 and 45 nm technology S Shaik, P Jonnala
2013 International Conference on Renewable Energy and Sustainable Energy …, 2013
21 2013 Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm H Vallabhaneni, A Japa, S Shaik, KSR Krishna, R Vaddi
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), 1-5, 2014
18 2014 Tunnel FET based low voltage static vs dynamic logic families for energy efficiency K Subramanyam, S Shaik, R Vaddi
18th International Symposium on VLSI Design and Test, 1-2, 2014
13 2014 High secure buffer based physical unclonable functions (PUF’s) for device authentication S Shaik, AK Kurra, A Surendar
TELKOMNIKA (Telecommunication Computing Electronics and Control) 17 (1), 377-383, 2019
12 2019 Circuit and architectural co-design for reliable adder cells with steep slope tunnel transistors for energy efficient computing S Shaik, KSR Krishna, R Vaddi
2016 29th International Conference on VLSI Design and 2016 15th …, 2016
12 2016 Sensors based automated wheelchair C Vijaya Kumar, M Pavan Kumar, S Sivaji, S Sadulla, J Prathiba, ...
Green Computing, Communication and Conservation of Energy (ICGCE), 2013 …, 2013
12 2013 Design and Performance Evaluation of Energy Efficient 8-Bit ALU at Ultra-Low Supply Voltages Using FinFET with 20 nm Technology V Vijay, PC Shekar, S Sadulla, P Manoja, R Abhinaya, M Rachana, ...
VLSI Architecture for Signal, Speech, and Image Processing, 67-85, 2022
10 2022 Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs G Kaushal, K Subramanyam, SN Rao, G Vidya, R Ramya, S Shaik, ...
2014 International SoC Design Conference (ISOCC), 32-33, 2014
9 2014 Statistical analysis of arbiter physical unclonable functions using reliable and secure transmission gates S Shaik, AK Kurra, A Surendar
International Journal of Simulation--Systems, Science & Technology 19 (4), 6 …, 2018
8 2018 Nano-scale Transistors with Circuit Interaction for Designing Energy-Efficient and Reliable Adder Cells at Low V DD S Shaik, K Sri Rama Krishna, R Vaddi
IETE Technical Review 35 (5), 456-466, 2018
7 2018 Wireless solution for polyhouse cultivation using embedded system P Jonnala, S Shaik
2013 International Conference on Renewable Energy and Sustainable Energy …, 2013
7 2013 Tunnel transistors with circuit co-design in designing reliable logic gates for energy efficient computing S Shaik, KSR Krishna, R Vaddi
2015 IEEE Asia Pacific Conference on Postgraduate Research in …, 2015
6 2015 Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low V S Shaik, KSR Krishna, R Vaddi
Journal of Circuits, Systems and Computers 27 (03), 1850046, 2018
5 2018