Yuko Hara-Azumi
Title
Cited by
Cited by
Year
Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis
Y Hara, H Tomiyama, S Honda, H Takada
journal of information processing 17, 242-254, 2009
2912009
CHStone: A benchmark program suite for practical c-based high-level synthesis
Y Hara, H Tomiyama, S Honda, H Takada, K Ishii
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on …, 2008
1712008
CGRA-ME: A unified framework for CGRA modelling and exploration
SA Chin, N Sakamoto, A Rui, J Zhao, JH Kim, Y Hara-Azumi, J Anderson
2017 IEEE 28th International Conference on Application-specific Systems …, 2017
282017
Profiling-driven multi-cycling in FPGA high-level synthesis
S Hadjis, A Canis, R Sobue, Y Hara-Azumi, H Tomiyama, J Anderson
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 31-36, 2015
172015
A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips
TA Dinh, S Yamashita, TY Ho, Y Hara-Azumi
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 199-204, 2013
132013
Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy
JH Anderson, Y Hara-Azumi, S Yamashita
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016
112016
Synthesizable-from-C embedded processor based on MIPS-ISA and OISC
T Ahmed, N Sakamoto, J Anderson, Y Hara-Azumi
2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing …, 2015
92015
Cost-Efficient Scheduling in High-Level Synthesis for Soft-Error Vulnerability Mitigation
Y Hara, H Tomiyama
International Symposium on Quality Electronic Design, 2013
9*2013
Function call optimization in behavioral synthesis
Y Hara, H Tomiyama, S Honda, H Takada
9th EUROMICRO Conference on Digital System Design (DSD'06), 522-529, 2006
82006
Instruction-set extension under process variation and aging effects
Y Hara-Azumi, F Firouzi, S Kiamehr, M Tahoori
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 182-187, 2013
72013
Partitioning of behavioral descriptions with exploiting function-level parallelism
Y Hara, H Tomiyama, S Honda, H Takada
IEICE Transactions on Fundamentals of Electronics Communications and …, 2010
72010
Function-level partitioning of sequential programs for efficient behavioral synthesis
Y Hara, H Tomiyama, S Honda, H Takada, K Ishii
IEICE transactions on fundamentals of electronics, communications and …, 2007
62007
Function call optimization for efficient behavioral synthesis
Y Hara, H Tomiyama, S Honda, H Takada
IEICE transactions on fundamentals of electronics, communications and …, 2007
62007
FPGA-Based Hardware/Software Co-Design of a Bio-Inspired SAT Solver
AHN Nguyen, M Aono, Y Hara-Azumi
IEEE Access 8, 49053-49065, 2020
52020
Impact of resource sharing and register retiming on area and performance of FPGA-based designs
Y Hara-Azumi, T Matsuba, H Tomiyama, S Honda, H Takada
Information and Media Technologies 9 (1), 26-34, 2014
52014
Task mapping techniques for embedded many-core socs
J Kaida, T Hieda, I Taniguchi, H Tomiyama, Y Hara-Azumi, K Inoue
2012 International SoC Design Conference (ISOCC), 204-207, 2012
52012
Selective resource sharing with RT-level retiming for clock enhancement in high-level synthesis
Y Hara-Azumi, T Matsuba, H Tomiyama, S Honda, H Takada
2012 IEEE 14th International Conference on High Performance Computing and …, 2012
52012
Clock-constrained simultaneous allocation and binding for multiplexer optimization in high-level synthesis.
Y Hara-Azumi, H Tomiyama
ASP-DAC, 251-256, 2012
52012
A circuit-level amoeba-inspired sat solver
N Takeuchi, M Aono, Y Hara-Azumi, CL Ayala
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (10), 2139-2143, 2019
42019
SSA-AC: Static significance analysis for approximate computing
SA Metwalli, Y Hara-Azumi
ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (3 …, 2019
42019
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Articles 1–20