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Jyoti Kandpal
Jyoti Kandpal
G.B. Pant University of Agriculture and Technology Pantnagar
Verified email at gbpuat.ac.in
Title
Cited by
Cited by
Year
High-speed hybrid-logic full adder using high-performance 10-T XOR–XNOR cell
J Kandpal, A Tomar, M Agarwal, KK Sharma
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (6 …, 2020
752020
Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications
J Kandpal, A Tomar, M Agarwal
Microelectronics Journal 115, 105205, 2021
152021
Design of low power and high speed XOR/XNOR circuit using 90 nm CMOS technology
J Kandpal, A Tomar, S Adhikari, V Joshi
2019 2nd International Conference on Innovations in Electronics, Signal …, 2019
102019
Design of low power and secure implementation of sbox for aes
H Prasad, J Kandpal, D Sharma, G Verma
2016 3rd International Conference on Computing for Sustainable Global …, 2016
52016
Integration of Artificial Intelligence with Opto-VLSI for the Biomedical and Healthcare Industries
J Kandpal, G Baluti, P Ranjan
Opto-VLSI Devices and Circuits for Biomedical and Healthcare Applications …, 0
2
Opto-VLSI Devices and Circuits for Biomedical and Healthcare Applications
A Kumar, S Agarwal, V Varshnay, V Mishra, YK Verma, SL Tripathi
CRC Press, 2023
12023
Conventional current reference generation strategies for grid-connected distributed energy sources
J Joshi, VP Dubey, J Kandpal, V Chamoli
2023 International Conference on Device Intelligence, Computing and …, 2023
12023
A variation resilient keeper design for high performance domino logic applications
J Kandpal, TR Pokhrel, S Saini, A Majumder
Integration 88, 1-9, 2023
12023
Machine learning for intelligent analytics
J Pokhariya, PK Mishra, J Kandpal
Advances in Cyber Security and Intelligent Analytics, 219-234, 2022
12022
A high-performance hybrid full adder circuit
MS Hussain, J Kandpal, M Hasan, M Muqeem
2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical …, 2022
12022
An energy efficient and fast hybrid full adder circuit
MS Hussain, J Kandpal, A Malik, M Hasan
2022 5th International Conference on Multimedia, Signal Processing and …, 2022
12022
Opportunity and Challenges for VLSI in IoT Application
J Kandpal, A Singh
5G Internet of Things and Changing Standards for Computing and Electronic …, 2022
12022
High performance 20-T based hybrid full adder using 90nm CMOS technology
J Kandpal, A Tomar, K Pandey, M Agarwal
2019 Women Institute of Technology Conference on Electrical and Computer …, 2019
12019
A sense-amplifier based flip-flop with symmetric latch design
K Pandey, A Tomar, J Kandpal
2019 Women Institute of Technology Conference on Electrical and Computer …, 2019
12019
Design of Low Power and Secure Implementation of SBox and Inverse-SBox for AES
D Sharma, A Bhardwaj, H Prasad, J Kandpal, A Saxena, KS Kant, ...
International Journal of Security and Its Applications 10 (7), 11-24, 2016
12016
Design and implementation of high-performance 20-T hybrid full adder circuit
J Kandpal, A Tomar
Analog Integrated Circuits and Signal Processing 119 (1), 97-110, 2024
2024
A Comprehensive Study on AlGaN/GaN-Based HEMT for High-Speed
J Kandpal, A Kumar
International Journal of High Speed Electronics and Systems, 2450001, 2024
2024
Simulation and Experiment Assisted Electronics Education in Electrical Engineering: A Case Study of an Experiment
Z Sifat, MS Hussian, MU Iqubal, J Kandpal
2023 International Conference on Next Generation Electronics (NEleX), 1-5, 2024
2024
Machine Learning–Based VLSI Test and Verification
J Kandpal
Machine Learning for VLSI Chip Design, 33-50, 2023
2023
Configuring a Hybrid Full Adder Using Strained-Si Channel DG JLT with Work Function Modulation
TR Pokhrel, J Kandpal, A Majumder
Silicon 15 (10), 4513-4519, 2023
2023
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