| Way-predicting set-associative cache for high performance and low energy consumption K Inoue, T Ishihara, K Murakami Proceedings of the 1999 international symposium on Low power electronics and …, 1999 | 445 | 1999 |
| Novel frontier of photonics for data processing—Photonic accelerator K Kitayama, M Notomi, M Naruse, K Inoue, S Kawakami, A Uchida Apl Photonics 4 (9), 2019 | 174 | 2019 |
| Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing Y Inadomi, T Patki, K Inoue, M Aoyagi, B Rountree, M Schulz, ... Proceedings of the international conference for high performance computing …, 2015 | 153 | 2015 |
| Multiplier energy reduction through bypassing of partial products J Ohban, VG Moshnyaga, K Inoue Asia-Pacific conference on circuits and systems 2, 13-17, 2002 | 116 | 2002 |
| Power and performance analysis of {GPU-Accelerated} systems Y Abe, H Sasaki, M Peres, K Inoue, K Murakami, S Kato 2012 Workshop on Power-Aware Computing and Systems (HotPower 12), 2012 | 88 | 2012 |
| Power and performance characterization and modeling of GPU-accelerated systems Y Abe, H Sasaki, S Kato, K Inoue, M Edahiro, M Peres 2014 IEEE 28th international parallel and distributed processing symposium …, 2014 | 84 | 2014 |
| Performance prediction of large-scale parallell system and application using macro-level simulation R Susukita, H Ando, M Aoyagi, H Honda, Y Inadomi, K Inoue, S Ishizuki, ... SC'08: Proceedings of the 2008 ACM/IEEE Conference on Supercomputing, 1-9, 2008 | 67 | 2008 |
| Proposal of a desk-side supercomputer with reconfigurable data-paths using rapid single-flux-quantum circuits N Takagi, K Murakami, A Fujimaki, N Yoshikawa, K Inoue, H Honda IEICE transactions on electronics 91 (3), 350-355, 2008 | 58 | 2008 |
| Coordinated power-performance optimization in manycores H Sasaki, S Imamura, K Inoue Proceedings of the 22nd international conference on Parallel architectures …, 2013 | 57 | 2013 |
| Scalability-based manycore partitioning H Sasaki, T Tanimoto, K Inoue, H Nakamura Proceedings of the 21st international conference on Parallel architectures …, 2012 | 56 | 2012 |
| Dynamically variable line-size cache exploiting high on-chip memory bandwidth of merged DRAM/logic LSIs K Inoue, K Kai, K Murakami Proceedings Fifth International Symposium on High-Performance Computer …, 1999 | 51 | 1999 |
| SuperNPU: An extremely fast neural processing unit using superconducting logic devices K Ishida, I Byun, I Nagaoka, K Fukumitsu, M Tanaka, S Kawakami, ... 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 48 | 2020 |
| Production hardware overprovisioning: Real-world performance optimization using an extensible power-aware resource management framework R Sakamoto, T Cao, M Kondo, K Inoue, M Ueda, T Patki, D Ellsworth, ... 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2017 | 45 | 2017 |
| An open source FPGA-optimized out-of-order RISC-V soft processor S Mashimo, A Fujita, R Matsuo, S Akaki, A Fukuda, T Koizumi, ... 2019 International Conference on Field-Programmable Technology (ICFPT), 63-71, 2019 | 38 | 2019 |
| 29.3 A 48GHz 5.6 mW gate-level-pipelined multiplier using single-flux quantum logic I Nagaoka, M Tanaka, K Inoue, A Fujimaki 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 460-462, 2019 | 36 | 2019 |
| Automatic arrival time detection for earthquakes based on stacked denoising autoencoder OM Saad, K Inoue, A Shalaby, L Samy, MS Sayed IEEE Geoscience and Remote Sensing Letters 15 (11), 1687-1691, 2018 | 32 | 2018 |
| 32 GHz 6.5 mW gate-level-pipelined 4-bit processor using superconductor single-flux-quantum logic K Ishida, M Tanaka, I Nagaoka, T Ono, S Kawakami, T Tanimoto, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 31 | 2020 |
| An architecture framework for an adaptive extensible processor H Noori, F Mehdipour, K Murakami, K Inoue, M Saheb Zamani The Journal of Supercomputing 45, 313-340, 2008 | 31 | 2008 |
| A history-based I-cache for low-energy multimedia applications K Inoue, VG Moshnyaga, K Murakami Proceedings of the 2002 international symposium on Low power electronics and …, 2002 | 29 | 2002 |
| A high-performance and low-power cache architecture with speculative way-selection K Inoue, T Ishihara, K Murakami IEICE transactions on electronics 83 (2), 186-194, 2000 | 29 | 2000 |
Kazuaki Murakami / 村上和彰Kyushu UniversityVerified email at ait.kyushu-u.ac.jp
